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Preliminary
MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor
Architecture Overview
Architecture Overview
Figure 4:
Block Diagram
Ima g e Flow Pro c essor
Interpolation
Line Buffers
De c imator
Line Buffers
JPE G
Line Buffers
Other JPE G
Memories
S ensor
C ore
PLL
C olor Pipeline
S tats En g ine
JPE G
F
I
F
O
Internal Re g ister Bus
ROM
Mi c ron
c ontroller
S RAM
Sensor Core
The MT9D131 sensor core is a 2-megapixel CMOS image sensor with a 2.8μm pixel size
designed for an optical format of 1/3.2 inches with a UXGA maximum resolution. The
MT9D131 sensor core includes a phase-locked loop oscillator (PLL), to facilitate camera
integration and minimize the system cost for wireless and mobile applications. When in
use, the PLL generates an internal master clock signal whose frequency can be set higher
than the frequency of external clock signal EXTCLK. This allows the MT9D131 to run at
any resolution and frame rate up to the specified maximum values, irrespective of the
EXTCLK frequency.
PDF: 09005aef824c90ce/Source: 09005aef824c90d6
MT9D131_LDS_2.fm - Rev. B 3/07 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2006 Micron Technology, Inc. All rights reserved.
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